20th International Conference
on Field Programmable Logic and Applications
Milano, ITALY, Aug. 31st - Sep. 2nd, 2010

Pre-conference workshops:

Post-conference workshops and tutorials:

Workshops and Tutorials

Altera Workshop - Enhancing Education with Altera's Technology and Teaching Materials

Date: August 30, 2010
Time: 9:00-17:00
Location: Politecnico di Milano, EG8, Campus Leonardo
Instructor: Tom Czajkowski

To Register (max. 20 participants) send an email to Tom at: tczajkow AT altera DOT com

This workshop introduces Altera's technology and teaching materials developed specifically for use in Digital Logic and Computer Organization courses. We will give an overview of Altera's FPGA technology, and its application in an educational setting. We will concentrate on the use of Quartus II software and a hardware platform based on Altera's DE1/DE2 boards. Participants will have an opportunity to implement logic circuits on these boards, which were designed for use in educational environments.

We will demonstrate how Quartus II CAD software can be used to design and implement logic circuits that can be downloaded onto a DE1/DE2 board. The discussion will include the use of debugging facilities included in Quartus II software, such as the RTL (Register Transfer Level) Viewer and the SignalTap II Embedded Logic Analyzer.

Next, we will discuss how a computer system can be implemented on the DE1/DE2 board. This involves using the System-on-Programmable-Chip (SOPC) Builder tool and the Nios II soft-core processor. We will show how application programs written in either the Nios II assembly language or the C programming language can be compiled, downloaded and run. This will be done with the Altera Monitor Program, which provides the facilities for implementation and debugging of application programs.

Finally, we will discuss advanced topics that include timing analysis and the design of embedded systems. We will show how timing analysis works, how to use the Altera TimeQuest Timing Analyzer, and apply timing constraints to user designs. For embedded systems, we will demonstrate the features of the SOPC Builder needed in designing embedded systems.

If attendees wish to use their own laptops during the workshop, then they should download and install software found at www.altera.com prior to the tutorial. In particular, attendees should download and install:
- Quartus II 9.1 web edition
- Nios II Embedded Design Suite 9.1
- Altera Monitor Program

The first two packages are available in the Download Center, which has a link at the top right corner of www.altera.com. The Altera Monitor Program is available on the University Program section of Altera's website. It can be found by opening the web page university.altera.com and clicking on the link called Design Software in the Educational Materials area of the web page.

We will provide Altera DE1 boards for use in the hands-on part of the tutorial.

At the end of the tutorial we will give away Altera DE1 boards to professors and instructors who attend the session

Synopsys Tutorial - High reliability and performance efficiencies in FPGA Design

Date: September 2, 2010
Time: 15:30-18:00
Location: Politecnico di Milano, Aula De Donato (ex S01), Campus Leonardo
Instructor: Massimo Prando

Online Registration (max. 30 participants)

Today's FPGAs are doubling in capacity every 2 years and will, by next year, surpass the 10 million equivalent ASIC gate mark. As a result, design runtimes have become a bottleneck - with iterations to debug and tune designs now consuming days. At the same time, FPGA use has expanded from telecommunications applications to high end consumer and high reliability applications. In addition, FPGAs may be used as prototypes for ASIC and ASSP applications. All this has led to the need for new design methodologies for FPGA design.

In this session, we will introduce techniques to use during FPGA design that will help you to...
- Cut FPGA design iteration runtimes and achieve results stability from one run to the next
- Improve design performance and device cost
- Perform safety-critical FPGA design – ensure traceability, repeatability, equivalence -- in high reliability applications
- Make architectural decisions about how to implement DSP designs
- Use FPGAs as prototypes for your ASIC or ASSP to eliminate hard to find bugs or to perform early system software development

Xilinx Workshop - Partial Reconfiguration Flow Workshop and Teaching Materials

Date: September 3 - 4, 2010
Time: Friday 8:30 - 19:00; Saturday 8:30 - 14:00
Location: Politecnico di Milano, EG8, Campus Leonardo
Instructor: Parimal Patel

Online Registration (max. 40 participants)

Xilinx University Program (XUP) is pleased to offer a new workshop on the 4th generation of Partial Reconfiguration technology.

This workshop introduces partial reconfiguration technology, discusses motivation for such technology, and illustrates typical applications where partial reconfiguration may be used. We will go through the intuitive design flow using built-in capabilities of the tools. In this workshop, we will use XUPV5 board to verify various designs you will develop using PlanAhead, EDK, and ChipScope Pro Analyzer tools.

For additional information and workshop registration, please visit www.xilinx.com/university/workshops/partial-reconfiguration-flow/index.htm.

Workshop Location

Workshops will be held in the EG8 room, located as shown in the map.