FPL2010 logo

20th International Conference
on Field Programmable Logic and Applications
Milano, ITALY, Aug. 31st - Sep. 2nd, 2010

Conference Technical Program

This is the detailed program of the conference. For each presented paper there is a PDF version of the presentation available for download.
Authors maintain the copyright and to use such material (allowed only for non-commercial purposes) the end-users must acknowledge the source.

Tuesday Aug. 31, 2010

9:00 - 9:20 Conference Opening

9:20 - 10:15 Keynote Talk
fos - Building a Self-Aware Operating System for Multicores and Clouds
Prof. Anant Agarwal (MIT) keynote presentation

10:15 - 10:50 Coffee & Poster Session I

An FPGA-based Transverse Multibunch Feedback System for Diamond Light Source
Isa Uzun, Mark Heron, Alun Morgan, and Guenther Rehm
Control Techniques for Coupling a Coarse-Grain Reconfigurable Array with a Generic RISC Core
Fabio Garzia, Waqar Hussain, and Jari Nurmi
Exploiting Dynamic Reconfiguration for FPGA Based Network Intrusion Detection Systems
Salvatore Pontarelli, Claudio Greco, Enrico Nobile, Simone Teofili, and Giuseppe Bianchi
A Scalable, High-Performance Motion Estimation Application for a Weakly-Programmable FPGA Architecture
Henning Sahlbach, Sean Whitty, Oliver Bende, and Rolf Ernst
Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic
Amit Verma, Ajay K. Verma, Hadi Parandeh-Afshar, Philip Brisk, and Paolo Ienne
An FPGA Based Hybrid Processor Emulation Platform
Qigang Wang, Rolf Kassa, Wenbo Shen, Nelson Ijih, Bhushan Chitlur, Michael Konow, Dong Liu, Arthur Sheiman, and Prabhat Gupta
Parallelizing Simulated Annealing-Based Placement Using GPGPU
Alexander Choong, Rami Beidas, and Jianwen Zhu
Efficiently Generating FPGA Configurations through a Stack Machine
Fatma Abouelella, Karel Bruneel, and Dirk Stroobandt

10:50 - 12:20 Regular Expression Matching on FPGA

Session chair: Koen Bertels, Technical University of Delft, The Netherlands

Optimization of Regular Expression Pattern Matching Circuit Using At-Most Two-Hot Encoding on FPGA
SangKyun Yun and KyuHee Lee
A Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression Matching
Francesco Bruschi, Marco Paolieri, and Vincenzo Rana
Automation Framework for Large-Scale Regular Expression Matching on FPGA
Thilan Ganegedara, Yi-Hua E. Yang, and Viktor K. Prasanna

10:50 - 12:20 Multimedia

Session chair: Tomasz Czajkowski, ALTERA

Real-Time Classification of Multimedia Traffic Using FPGA
Weirong Jiang and Maya Gokhale
Parallel Hardware Implementation of Connected Component Tree Computation
Petr Matas, Eva Dokladalova, Mohamed Akil, Vjačeslav Georgiev, and Martin Poupa
no presentation available
Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs
Andrés Otero, Eduardo de la Torre, Teresa Riesgo, and Yana E. Krasteva

10:50 - 12:20 Random Numbers and Cryptography

Session chair: Mario Porrmann, University of Paderborn, Germany

FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers
winner of the Stamatis Vassiliadis award
David B. Thomas and Wayne Luk
High-Performance Integer Factoring with Reconfigurable Devices
Ralf Zimmermann, Tim Güneysu, and Christof Paar
Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA
Chalermpol Saiprasert, Christos-Savvas Bouganis, and George A. Constantinides

12:20 - 13:30 Lunch

13:30 - 15:00 Scheduling

Session chair: David Thomas, Imperial College, UK

Advanced Multithreading Architecture with Hardware Based Scheduling
Ye Lu, Sakir Sezer, and John McCanny
Thermal Gradient Aware Clock Skew Scheduling for FPGAs
Sungmin Bae and N. Vijaykrishnan
A Reconfigurable Computing Scheduler Optimized for Multicore Systems
Philip Garcia, Kyle Rupnow, and Katherine Compton

13:30 - 15:00 GPU, CPU and FPGA

Session chair: Donatella Sciuto, Politecnico di Milano, Italy

An Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs
Brian Leung, Chih-Hung Wu, Seda Ogrenci Memik, and Sanjay Mehrotra
GPU Versus FPGA for High Productivity Computing
David H. Jones, Adam Powell, Christos-Savvas Bouganis, and Peter Y.K. Cheung
Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs)
Doris Chen and Deshanand Singh

13:30 - 15:00 Reconfigurable Architecture and Cryptography

Session chair: Udo Kebschull, Heidelberg University, Germany

Breaking Elliptic Curve Cryptosystems Using Reconfigurable Hardware
Junfeng Fan, Daniel V. Bailey, Lejla Batina, Tim Güneysu, Christof Paar, and Ingrid Verbauwhede
Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures
Lyonel Barthe, Pascal Benoit, and Lionel Torres
Implementing Rainbow Tables in High-End FPGAs for Super-Fast Password Cracking
Kostas Theocharoulis, Ioannis Papaefstathiou, and Charalampos Manifavas

15:00 - 15:30 Coffee & Poster Session II

Detecting Patterns in Various Size and Angle Using FPGA
Masayuki Suzuki, Yoshifumi Tanida, and Tsutomu Maruyama
Real-Time Processing of Contrast Limited Adaptive Histogram Equalization on FPGA
Kentaro Kokufuta and Tsutomu Maruyama
Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC
Hung-Manh Pham, Sebastien Pillement, and Didier Demigny
Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine
Stephen Wray, Wayne Luk, and Peter Pietzuch
Sum of Absolute Difference Implementations for Image Processing on FPGAs
Hiroaki Niitsuma and Tsutomu Maruyama
Pixel Similarity Based Computation and Power Reduction Technique for H.264 Intra Prediction
Yusuf Adıbelli, Mustafa Parlak, and İlker Hamzaoğlu
Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters
Amir Hossein Gholamipour, Fadi Kurdahi, Ahmed Eltawil, and Mazen A.R. Saghir
Secure Protocol Implementation for Remote Bitstream Update Preventing Replay Attacks on FPGA
Florian Devic, Lionel Torres, and Benoît Badrignans
Online Routing Fault Detection for Reconfigurable NoC
C. Killian, C. Tanougast, F. Monteiro, and A. Dandache

15:30 - 17:00 Self-Aware and Adaptable Systems

Session chair: Michael Hubner, University of Karlsruhe, Germany

Self-Aware Adaptation in FPGA-based Systems
F. Sironi, M. Triverio, H. Hoffmann, M. Maggio, and M.D. Santambrogio
Self-Test and Adaptation for Random Variations in Reliability
Kenneth M. Zick and John P. Hayes
Memory System for a Dynamically Adaptable Pixel Stream Architecture
Nicolas Ngan, Geoffroy Marpeaux, Eva Dokladalova, Mohamed Akil, and François Contou-Carrère

15:30 - 17:00 Reconfigurable and Customized Processors

Session chair: David Jones, Imperial College London, UK

Test Compression for Dynamically Reconfigurable Processors
Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, and Koichiro Furuta
A Reconfigurable Analog Processor Based on FPAA with Coarse-Grained, Heterogeneous Configurable Analog Blocks
Wen-Hui Fu, Jun Jiang, Xi Qin, Ting Yi, and Zhi-Liang Hong
Customized Exposed Datapath Soft-Core Design Flow with Compiler Support
Otto Esko, Pekka Jääskeläinen, Pablo Huerta, Carlos S. de La Lama, Jarmo Takala, and Jose Ignacio Martinez

15:30 - 17:00 Communication Infrastructure

Session chair: David Atienza, EPFL, Switzerland

A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier
Heiner Giefers and Marco Platzner
Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers
Leandro Möller, Peter Fischer, Fernando Moraes, Leandro Soares Indrusiak, and Manfred Glesner
A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs
Andreas Oetken, Stefan Wildermann, Jürgen Teich, and Dirk Koch

17:00 - 17:30 PhD Forum & Welcome Drink

Session chair: Giovanni Squillero, Politecnico di Torino, Italy

Design and Implementation of an Object-Oriented Framework for Dynamic Partial Reconfiguration
Norbert Abel
Erlang Inspired Hardware
Paulo Ferreira, João Canas Ferreira, and José Carlos Alves
IP Based Configurable SIMD Massively Parallel SoC
Mouna Baklouti, Mohamed Abid, Philippe Marquet, and Jean Luc Dekeyser
FPGA Based Engines for Genetic and Memetic Algorithms
Pedro V. Santos and José C. Alves
Proof-Carrying Hardware: Runtime Formal Verification for Secure Dynamic Reconfiguration
Stephanie Drzevitzky
Robust FPGA Design under Variations
Akhilesh Kumar and Mohab Anis
On Identifying Segments of Traces for Dynamic Compilation
João Bispo and João M.P. Cardoso
On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates
Adriano Sanches and João M.P. Cardoso

19:30 Visit to Leonardo’s Last Supper

Wednesday Sep. 1, 2010

8:45 - 9:40 Keynote Talk
The Field Programmable Logic Perspective
Dr. Patrick Lysaght (Xilinx) keynote presentation

9:45 - 11:15 Memories and Application Interfaces

Session chair: Francesco Bruschi, Politecnico di Milano, Italy

Software Managed Distributed Memories in MPPAs
Robin Panda, Jimmy Xu, and Scott Hauck
Design and Implementation of Real-Time Transactional Memory
Martin Schoeberl and Peter Hilber
Rapid Application Development on Multi-processor Reconfigurable Systems
Linfeng Ye, Jean-Philippe Diguet, and Guy Gogniat

9:45 - 11:15 New Trends and Solutions in
Programmable Logic

Session chair: Katherine Compton, University of Wisconsin-Madison, USA

Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs
Syed Zahid Ahmed, Gilles Sassatelli, Lionel Torres, and Laurent Rougé
First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, and Toshinori Sueyoshi
COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization
Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, and Toshinori Sueyoshi

9:45 - 11:15 Design Methodologies and Tools

Session chair: Martin Danek, UTIA AV CR, Czech Republic

PrEsto: An FPGA-accelerated Power Estimation Methodology for Complex Systems
Dam Sunwoo, Gene Y. Wu, Nikhil A. Patil, and Derek Chiou
Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains
winner of the Michael Servit award
Thomas B. Preußer and Rainer G. Spallek

Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA
F. Restrepo-Calle, A. Martínez-Álvarez, F.R. Palomo, H. Guzmán-Miranda, M.A. Aguirre, and S. Cuenca-Asensi

11:15 - 11:45 Coffee & Poster Session III
A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs
Marcus Ritt, Carlos Arthur Lang Lisboa, Luigi Carro, and Cristiano Lazzari
Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique
Antonín Heřmánek, Michal Kuneš, and Milan Tichý
Generation of Deterministic MCU/FPGA Hybrid Systems from UML Activities
Ruediger Willenberg, Zamira Daw, Christian Englert, and Marcus Vetter
Real-Time Fault Detection and Diagnostics Using FPGA-based Architectures
Nathan Naber, Thomas Getz, Yong Kim, and James Petrosky
A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems
Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, and Hiroaki Takada
NIFD: Non-intrusive FPGA Debugger -- Debugging FPGA ‘Threads’ for Rapid HW/SW Systems Prototyping
Hari Angepat, Gage Eads, Christopher Craik, and Derek Chiou
Exploration of Short Reads Genome Mapping in Hardware
Edward Fernandez, Walid Najjar, Elena Harris, and Stefano Lonardi
Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options
Anson H.T. Tse, David B. Thomas, K.H. Tsoi, and Wayne Luk

11:50 - 12:45 Keynote Talk
Customising field programmability
Prof. Wayne Luk (Imperial College London) keynote presentation

12:50 - 13:55 Lunch

14:00 - 15:30 Reconfigurable Technology

Session chair: Parimal Patel, Xilinx, USA

Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA
Vijay K. Sirigir, Khawla Alzoubi, Daniel G. Saab, Fatih Kocan, and Massood Tabib-Azar
no presentation available
High Density Asynchronous LUT Based on Non-volatile MRAM Technology
Sumanta Chaudhuri, Weisheng Zhao, Jacques-Oliver Klein, Claude Chappert,and Pascale Mazoyer
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays
Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, and Scott Hauck

14:00 - 15:30 Applications

Session chair: Lionel Torres, LIRMM CNRS / University of Montpellier, France

Design and FPGA Implementation of a 2nd Order Adaptive Delta Sigma Modulator with One Bit Quantization
Shahrukh Athar, Muhammad Ali Siddiqi, and Shahid Masud
Decision Forest: A Scalable Architecture for Flexible Flow Matching on FPGA
Weirong Jiang, Viktor K. Prasanna, and Norio Yamagaki
FPGA Implementations of the Round Two SHA-3 Candidates
Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Maire O'Neill, and William P. Marnane

14:00 - 15:30 Benchmarking and Architecture Evaluation

Session chair: João Cardoso, FEUP/University of Porto, Portugal

ERCBench: An Open-Source Benchmark Suite for Embedded and Reconfigurable Computing
Daniel W. Chang, Christipher D. Jenkins, Philip C. Garcia, Syed Z. Gilani, Paula Aguilera, Aishwarya Nagarajan, Michael J. Anderson, Matthew A. Kenny, Sean M. Bauer, Michael J. Schulte, and Katherine Compton
ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs
winner of the FPL Community award
Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, and Benjamin Y. Brewster
Pipelined FPGA Adders
Florent de Dinechin, Hong Diep Nguyen, and Bogdan Pasca

15:30 - 16:00 Coffee & Poster Session IV
Degradation Analysis and Mitigation in FPGAs
Edward Stott, Justin S.J. Wong, and Peter Y.K. Cheung
A Karatsuba-Based Montgomery Multiplier
Gary C.T. Chow, Ken Eguro, Wayne Luk, and Philip Leong
Using Hard Macros to Reduce FPGA Compilation Time
Christopher Lavin, Marc Padilla, Subhrashankha Ghosh, Brent Nelson, Brad Hutchings, and Michael Wirthlin
SeqHive: A Reconfigurable Computer Cluster for Genome Re-sequencing
Kristian Stevens, Henry Chen, Terry Filiba, Peter McMahon, and Yun S. Song
Reconfigurable Systems for the Zuker and Predator Algorithms for Secondary Structure Prediction of Genetic Data
Miltiadis Smerdis, Panagiotis Dagritzikos, Grigorios Chrysos, Euripides Sotiriades,and Apostolos Dollas
LavA: An Open Platform for Rapid Prototyping of MPSoCs
Matthias Meier, Michael Engel, Matthias Steinkamp, and Olaf Spinczyk
OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices
Mingjie Lin, Ilia Lebedev, and John Wawrzynek
Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA
Ghizlane Lhairech-Lebreton, Philippe Coussy, and Eric Martin
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Gerald Hempel, Christian Hochberger, and Andreas Koch

16:00 - 17:00 HLL-based Design

Session chair: Jari Nurmi, Tampere University of Technology, Finland

A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation
Hagen Gädke-Lütjens, Benjamin Thielmann, and Andreas Koch
Early Prediction of Hardware Complexity in HLL-to-HDL Translation
Alessandro Cilardo, Paolo Durante, Carmelo Lofiego, and Antonino Mazzeo

16:00 - 17:00 Arithmetic Units

Session chair: Apostolos Dollas, Technical University of Crete, Greece

An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier
Malte Baesler, Sven-Ole Voigt, and Thomas Teufel
Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation
Gustavo Sutter, Jean-Pierre Deschamps, and José Luis Imaña

16:00 - 17:00 Special Applications

Session chair: Lesley Shannon, Simon Fraser University, Canada

Accurate Time-to-Digital Converter Based on Xilinx’s Digital Clock Managers
Ángel Quirós-Olozábal, Ma de los Ángeles Cifredo-Chacón, and José María Guerrero-Rodríguez
Dynamically Reconfigurable Vision-Chip Architecture
Maki Yasuda and Minoru Watanabe

19:00 Social Event at Museo della Scienza e della Tecnologia

Thursday Sep. 2, 2010

9:00 - 9:55 Keynote Talk
FPGAs at 28nm: Meeting the Challenge of Modern Systems-on-a-Chip
Dr. Vaughn Betz (Altera) keynote presentation

10:00 - 11:30 Reconfigurable Hardware for Networking

Session chair: Vincenzo Rana, Politecnico di Milano, Italy

Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration
Christopher Neely, Gordon Brebner, and Weijia Shang
FPGA Based Network Traffic Analysis Using Traffic Dispersion Patterns
Faisal Khan, Maya Gokhale, and Chen-Nee Chuah
Reconfigurable Hardware for Power-over-Fiber Applications
Michael Dreschmann, Michael Hübner, Moritz Röger, Oliver Sander, Christos Klamouris, Jürgen Becker, Wolfgang Freude, and Juerg Leuthold

10:00 - 11:30 Synthesis and Placement

Session chair: Antonio Miele, Politecnico di Milano, Italy

Efficient FPGA Resynthesis Using Precomputed LUT Structures
Andrew Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, and Arun Kundu
Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis
Adam Arnesen, Kevin Ellsworth, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent Nelson, Michael Rice, and Michael Wirthlin
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement
Farnaz Gharibian, Lesley Shannon, and Peter Jamieson

10:00 - 11:30 FPGA-based Accelerators

Session chair: Fabio Garzia, TUT, Finland

FPGA-accelerated Attractor Computation of Scale Free Gene Regulatory Networks
Ricardo Ferreira and Julio C. Goldner Vendramini
A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis
Bo Yu, Terrence Mak, Xiangyu Li, Fei Xia, Alex Yakovlev, Yihe Sun, and Chi-Sang Poon
An FPGA-based High-Speed, Low-Latency Processing System for High-Energy Physics
Stefan Kirsch, Felix Rettig, Dirk Hutter, Jan de Cuveland, Venelin Angelov, and Volker Lindenstruth

11:30 - 12:00 Coffee & Poster Session V
FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators
Muhammad Shafiq, Miquel Pericàs, Nacho Navarro, and Eduard Ayguadé
Multiplicative Square Root Algorithms for FPGAs
Florent de Dinechin, Mioara Joldes, Bogdan Pasca, and Guillaume Revy
A Compact Transactional Memory Multiprocessor System on FPGA
Matteo Pusceddu, Simone Ceccolini, Gianluca Palermo, Donatella Sciuto, and Antonino Tumeo
Field Programmable Gate Array Implementation of Parts-Based Object Detection for Real Time Video Applications
Deborah Goshorn, Junguk Cho, Ryan Kastner, and Shahnam Mirzaei
General Purpose Computing with Reconfigurable Acceleration
Anthony Brandon, Ioannis Sourdis, and Georgi N. Gaydadjiev
MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology
Sascha Mühlbach, Martin Brunner, Christopher Roblee, and Andreas Koch
Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration
Christian Beckhoff, Dirk Koch, and Jim Torresen
Dynamic Reconfiguration Optimisation with Streaming Data Decompression
Atukem Nabina and Jose L. Nuñez-Yañez
Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video
Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, and Masahiko Yoshimoto

12:00 - 12:45 Keynote Talk
On the bright future of hardware acceleration
Dr. Alessandro Forin (Microsoft Research) keynote presentation

12:45 - 13:15 Invited Talk
FPL-Benchmark Suite
Andreas Beyer, Udo Kebschull invited presentation

13:15 - 13:30 Closing Remarks

13:30 - 14:30 Lunch